There are many implementation for on-chip networks. However, so far I only see mesh or irregular network topology despite that other typologies has been presented in literature. Therefore, are you aware of any other implemented regular NoC topology?
there was some topics in literature addressing different NoC toplogy like ring, tree and tours , or Hierarchical ring, or Hierarchical tree, my work in process variability shows that Hierarchical topologies are more immune to process variations than the regular mesh.
E. K. Gawish , Variability-tolerant Networks on Chip, Text book, LAP Lambert Academic Publishing, April 2015
F. Gilabert, S. Medardoni, C. Gomez, M. E. Gomez, P. Lopez, G. N."tree topologies for regular network-on-chip design under nano scale constraints", Design Automation and Test in Europe Conference and Exhibition (DATE 2009), Nice,April 2009, pp. 562―565.
C. Fallin, X. Yu, K. Chang, R. Ausavarungnirun, and R. Das, “HiRD: A Low-Complexity, Energy-Efficient Hierarchical Ring Interconnect,” SAFARI Technical Report, December 2012, No. 2012-004.
Thanks, I am aware of literature discussing other topology. However, I would like to know if any has been implemented of fabricated? so far I only found Mesh topology such as the SCC prototype introduced by Intel.
I think fillan work contains performance comparison, but it may be only prototype, not full product
As far as I know, the Intel Xeon Phi series have utilized ring topology.
This answer may come a little late, but here's my take.
Apart from what the other fellows suggested, let me point to the following papers which have apparently been prototyped at least:
> This with a very high-radix topology > K. Sewell, R. G. Dreslinski, T. Manville, S. Satpathy, N. Pinckney, G. Blake, M. Cieslak, R. Das, T. F. Wenisch, D. Sylvester, D. Blaauw, and T. Mudge, “Swizzle-Switch Networks for Many-Core Systems,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 2, no. 2, pp. 278–294, Jun. 2012.
> This is a mesh, but implements different interesting improvements > B. Daya, C.-H. O. Chen, S. Subramanian, W.-C. Kwon, S. Park, T. Krishna, J. Holt, A. P. Chandrakasan, and L.-S. Peh, “SCORPIO: a 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering,” in Proceedings of the ISCA-41, 2014, pp. 25–36.
Many thanks Sergi for pointing outs these interesting NoC prototypes
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