Cadence is a very useful tool and provides many automated features that makes life a lot easier and faster. However, I could not figure out a way for measuring propagation delay values given digital inputs and outputs. The function 'cross' in the calculator is capable of detecting the timelapse of the first (or nth) high/low swing for a waveform, but this alone is not good enough at all.
Say there is a black box circuit, has 3 inputs A, B, C and 3 outputs X, Y, Z. I need to measure the worst case propagation delay for each of the outputs, so I definitely need some input combinations and transitions. Given that there are three inputs, there are 23 = 8 combinations, which makes 28 = 512 transition scenarios (e.g. 010 --> 110). In case of three outputs, I need a tool that tells me tp(X), tp(Y) and tp(Z) out of all these combinations for each of them. Does anybody have an idea for how to do this?
"Clip" the signal according to the timeslot you want to look at and use the "delay"-function with either edge...
Or build some simple logic around it with ideal components?!
I assume that you're using Spectre simulator with pwl generators as inputs to your CMOS circuit with rail-to-rail voltages (e.g. 0 to Vdd and viceversa). Another possibility, other than the one suggested by Felix, is that you define two parameters for all your generators, which is the initial voltage Vinit (0 or Vdd) of the pwl, and the final voltage Vend (also 0 or Vdd). Then you run a parametric analysis with all the possible combinations of the parameters (256 combinations) and save the delay for all of them.
Usually i would write a simple verilogAMS module to generate a input sequence, but in this case it can be done with standard elements only. Add a running variable, e.g. "run" to your variables. This is used to generate your input transitions. The 3 least significant bits of "run" now represent your input vector after the transition, whereas bits 3 to 5 represent the input vector before the transistion. Now place 3 puls sources "vpulse" from the analogLib for your input bits. The parameters have to be set as the following:
V0:
Voltage 1= vdd*((run/8)&1)
Voltage 2= vdd*(run&1)
V1:
Voltage 1= vdd*(((run/8)&2)>>1)
Voltage 2= vdd*((run&2)>>1)
V2:
Voltage 1= vdd*(((run/8)&4)>>2)
Voltage 2= vdd*((run&4)>>2)
Additionally you can add a delay time, which you have to consider in your analysis with the "cross"-function.
And also, rise, resp. fall time has to be set in order to override the standard setting.
Now run a parametric analysis over variable "run" with a range from 0 to 63 and step size 1. A disadvantage of this approach might be, that also cases with no transitions e.g. 000 --> 000 are simulated.
Regards, Marko
If the design is actually digital (I mean built from standard cells and synthesized with e.g. RC tool) you should validated it by specifying constraints that will be applied in Static Timing Analysis which performed by RC tool.
If the design is actually analog (I mean full-custom, transistor level) you should run corner and statistical analysis to account for process variations.
Like Marko proposed, I would also write a small VerilogA(MS) module, which generates all required input transitions as a sequence in time. You can use parameters to define rise/fall time, VDD and so on. Then, you simulate your circuit in a single transient simulation (512 transisions isn't really much). Then you can use the eyeDiagram function from the calculator to plot your output signal. Set the period equal to your transition cycle time and you can very easily obtain the worst and best case propagation delay.
If you don't like a graphical approach, you might write a skill function which extracts the worst case delay from your output signal.
By the way, this approach also allows Corner and Monte Carlo simulation. Only: Mind the correct load capacitance in your test bench! Might even be parameterized as well...
Thank you very much for all answers. I had some hard time generating a VerilogA module as I'm new to that, so I developed another methodology that provides very accurate results and takes very little time. Using the outputs of the 'cross' function of ADE XL tool, propagation delay measurement can be automated by processing the results in MS Excel. I also prepared a report of my methodology (attached), I'm happy to share it, I hope it would give insight to fellow researchers that experience similar problems.
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