--------------------------------------------------------------------------------
-- Company:
--
-- File: counter.vhd
-- File history:
-- : :
-- : :
-- : :
--
-- Description:
--
--
--
-- Targeted device:
-- Engineer:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- counter port starts
entity counter is
port (
rst : IN std_logic; -- reset
clk : IN std_logic; -- clock
--o_u : OUT std_logic_vector(3 downto 0); -- out
FPGA_IO_D00 :OUT std_logic;
FPGA_IO_D01 :OUT std_logic;
FPGA_IO_D02 :OUT std_logic;
FPGA_IO_D03 :OUT std_logic;
FPGA_IO_D04 :OUT std_logic;
FPGA_IO_D05 :OUT std_logic;
FPGA_IO_D06 :OUT std_logic;
FPGA_IO_D07 :OUT std_logic;
FPGA_IO_D08 :OUT std_logic;
FPGA_IO_D09 :OUT std_logic;
FPGA_IO_D10 :OUT std_logic;
FPGA_IO_D11 :OUT STD_LOGIC;
FPGA_IO_D12 :OUT std_logic;
FPGA_IO_D13 :OUT std_logic;
FPGA_IO_D14 :OUT std_logic;
FPGA_IO_D15 :OUT std_logic
);
end counter;
---a1: top_fpga port map()
architecture architecture_counter of counter is
signal count_signal : std_logic_vector(3 downto 0) ;
begin
process(rst,clk)
begin
if (rst='1') THEN count_signal
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