1)  1D FFT on each row

2)  1D FFT on each column resulting from (1) 

Check out the image processing IP core examples on the Xilinx website.  They are great templates to launch your project.  Just verify the size of your image and the speed which will determine which FPGA will work.

You need to use FPGA block ram to store your image if you have high end FPGA, then build a VHDL-based controller to fed the FFT core with the image pixels. IF your FPGA dose not provided with enough Ram, usually, FPGA boards are provided with SRAM that should be enough to store your image, then do the same thing by building a VHDL controller to control data transfer.

Altium Nanoboard could be a good choice to implement this, since you can import the FFT core to the schematic page.