Perhaps, Silvaco's tools is a better simulation basis for this type of study:
3D FinFET Simulation - Silvaco https://www.silvaco.com/examples/tcad/section29/example21/index.htmlmos2ex21.in : 3D FinFET Simulation. Requires: Victory Process, Victory Mesh, Victory Device ... Silvaco Inc., 2019 go victoryprocess init silicon layout=mos2ex21.lay depth=0.45 gasheight=1 line x location=0 line x location=0.0575 line x location=0.0595 line x location=0.05975 line x location=0.06 line x location=0.09 line x location=0.09025 ...
7nm pFinFET With SiGe Source-Drain Stressors - Silvaco https://www.silvaco.com/examples/tcad/section23/example26/index.htmlIn this example, we show the effects of mobility enhancement using epitaxially grown SiGe source-drain regions in a 7nm p-channel FinFET. The stress calculation is invoked during the process simulation with the Stress exposed statement line. This calculates the stress induced by the SiGe …
(PDF) Beyond silicon: Strained-SiGe channel FinFETs https://www.researchgate.net/publication/303013402...strained-SiGe channel FinFET technology is suitable for beyond 10nm CMOS manufacturing – pushing th e device scaling beyo nd the current l eading-edge volume prod uction