I am working on a standalone DC Microgrid with PV and Battery with a load interfaced to a common DC bus through power electronic interfaces. The interface of battery is a non-isolated bidirectional DC-DC converter, through which the DC bus voltage is being regulated at a reference value(48 V in our case). Now under the case of variable irradiance and variable load, I am experiencing spikes in voltage especially at the instants of load changes. The filter design of the power electronic interfaces has been proper. Can someone help me in solving this problem?
The DC bus voltage variation is attached. The loading pattern is also attached.
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It is necessary to add a PI regulator and adjust its parameters in order to reduce these voltage peaks in the DC-DC converter control.
You can try the following :
1: Try to increase the storage size up to the power rating of PV.
2: Try to understand the rate at which load or solar irradiance is changing.
3: Battery dynamic response is slower as compared to that of supercapacitors, use supercapacitor instead of a battery, it will quickly regulate the DC bus voltage at a nominal value.
Adding PI controller in the DC-DC converter circuit will reduce these spikes.
You don't mention where the voltage spikes are being measured, nor the length of the microgrid distribution lines. Those voltage spikes look to me like inductive voltage 'kicks' at the load end of a line due to the load current's dI/dt, without significant capacitance on the load end.
Parallel wires will have a transmission line impedance of a few 100 ohms (depending a bit on wire diameter, spacing and insulation), while your load impedance (V/I, or V2/P) ranges from around 2 to 20 ohms, so the distribution lines will definitely look inductive. This inductance will be a minimum of about 300 nH/foot, or 300 µH/1000', and could be twice that if the wires are not close together.
The worst case voltage spike shown of 20 V is for a load change of about 600 W, or say a 12 A current change. For a 300 µH line inductance, a 20 V spike would occur if the 12 A current change occurred over 180 us, or 0.18 ms. This is a lot faster than evident from your power vs time plot, but that may be limited by the risetime of your instrument.
As you can see, determining whether this is the problem would require more information, but it seems a very reasonable possibility. If this is the source of the voltage spikes, the best solution would be to install some "large can" 75V or 100 V electrolytic capacitors at the load(s), whose ESR would also help dampen any ringing.
The capacitance "C" required can be estimated from the line inductance "L" through the surge impedance Z = (L/C)1/2. For the assumed example (L = 300 uH, delta I = 12 A), lowering the 20 V spike to 6 V (Z = 6V/12A = 0.5) would require C = 1,200 uF. Lowering the voltage spike to 3 V would require 4 times the capacitance, or 4,800 uF.
It's worth a try.