To include the effect of process variation, I assumed a 10% variation in the width (W) of each transistor (each transistor has independent gaussian distribution with three sigma values) in an analog circuit.
Some suggestions mentioned about the Monte-Carlo model include intra- and inter-die variations. But I could not find any monte-carlo models for 32nm Low power PTM. Is varying the W-values a correct methodology? Also, any suggestions to include the Intrinsic manufacturing variation in HSPICE simulations for an analog circuit?
Dear Gisha C G,
Many years ago, I had co-authored the article facing a similar problem:
https://www.researchgate.net/publication/3283322_Prediction_of_Product_Yield_Distributions_from_Wafer_Parametric_Measurements_of_CMOS_Circuits
That time I used a bivariate Gaussian distribution analysis. You may want to look it over.
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