The simple way would seem to be to 'and' the output with the clock so that, when the clock is low, so is the output and when the clock is high, the output follows the PRBS.

That would be an asynchronous solution though. If you want it to be synchronous, you need to run another D-type as a simple toggle and use it both to enable your PRBS (to halve the rate) and again to 'and' with the output.

Sorry, I'm a VHDL guy so I'll leave turning that into Verilog to you but it shouldn't be too hard.

HTH

U can use if else condition statement  then that will work fine

use of if-else will be the solution.

but to get proper and exact output, design a state machine FSM(4 states for 4bits) and call function in each state. As it is output of d-ff, it is synchronous.

function should contain the logic for NZ 

Thanks George Dishman and all the contributors.