Unless you you understand the HDL well enough to calculate the latency from the input size, you generally have to run the algorithm, either in simulation or hardware, and measure the number of cycles of latency taken for different input sizes. Given the latency measurements, you can calculate throughput.

 Dear Lavanya,

Adding to Jamey, you can increase the operating clock frequency till the output logic value becomes in error. This can be made easily by comparing the output with expected correct output. When bit error begins this means the highest clock speed of the system is reached. Looking now to the no. of input bits per one clock cycle, which is is a system property, then one can get the highest input bit rate by multiplying the input bits per cycle times the highest clock speed. This is the throughput of the system.

Throughput= No of bits per one clock cycle x the highest clock speed

The highest clock speed can be calculated from the latency since highest clock speed= 1/latency

best wishes

A logic synthesis tool which is called  XST is integrated in Xilinx ISE. When the synthesis is completed,  the log will demonstrate the synthesis report in which you can see the max frequency and the critical path. 

Dear,

By using the Xilinx supplied synthesis engine known as XST. XST takes as input a verilog (.v) file and generates a .ngc file. A synthesis report file (.srp) is also generated, which describes the logic inferred for each part of the HDL file, and often includes helpful warning messages.

Thank you sir. I use only simulation tool ie. Isim. From simulation waveform one clock cycle was 20ns but i find that during synthesis xilinx gives timing summary as Minimum period: 6.842ns (Maximum Frequency: 146.149MHz).  There is a contradiction of which one to use to calculate latency.

In my opinion, the synthesis report is correct and is what should be concerned. 

Thank you all for your suggestions. Thanks Jamey sir and Zefry sir.

i suggest you to use the P&R  to estimate the maximum clock frequency, The Maximum frequency provided after the synthesis is less realistic

The maximum clock frequency is estimated in the place & route process. Usually, designer force a constraint and the software that performs P&R tries to satisfy it. In other words, if you want your design to reach 100 MHz, constraint the clock to this frequency (a bit more is better) and ISE or Vivaado try to satisfy your request.

Once you have the clock speed, you can estimate the throughput multiplying it by the number of involved bits.

I suggest you to consider the P&R report (here you can find the timing info if you have constrained the clock)instead of the synthesis report , the placing and the routing of the CLBimpacts on the propagation time. Simulation does not give you any information especially if you use behavioral simulation in which you can provide any value at the clock speed

Ms Lavanya

Hope this is useful to you. Latency is the delay before a transfer of data begins following an instruction for its transfer. Somewhere in your design if a worst path appear from one flop to another that requires minimum period i.e latency for that worst path and also results in maximum frequency. In general maximum frequency is not much use, because it will not give exact information on which clock is limited to that frequency under multi clock environment. But your throughput involves with number of cycles required to run your code, which can be observed from CPU time to Xst completion.

Luca Di Nunzio Sir, Can we consider the synthesis report generated by Genus or DC 180nm and 45nm instead of Xilinx synthesis report? How accurate are those?