The pipe line is built from processors working in tandem. As the number of processors increases,to perform some tasks such as MAC, the rate of processing gets higher as there are more processors working to perform the tasks. Concerning timing of the stages in the pipe line, The complete time required to perform the task is divided into processing cycle phases which means that the whole cycle time is divided among the stages according to their time need. So, if there is n stages and every stage requires processing time= Ti then the processing cycle time T= Sum of Ti from 1 to n.

This concerns the timing of the pipeline stages.These times can be estimated also by the required number of clock cycles by dividing Ti by the clock time Tck. 

Ti in clock cycles= Ti/Tck,

The clock cycle time is determined by the technology of the chip either dsp or fpga.

wish you success

In other words the frequency will be the reciprocal of maximum time taken by any processing stage (the maximum time delay from output of one  to output of another register, including combinational delays), The main problem is, how can we know the combinational path delays for the code that we write in verilog.

Eg : If I am prioritizing outputs of a register depending on a few signals.

always@(posedge clk)

begin

            if(reset)

                     dout

You told that you looked at the timing report after place and route. This report should show you the timing a signal needs to travel between two stages of your pipeline. the time given is quite a good measure of the cycle-time you can achieve with your design. The timing equations used are normally build for the nominal case. A cooler chip would improve the cycle-time.  However if you want to improve the cycle time by changes in the design, e.g. add an other pipeline stage or move logic between stages, the timing report is the best tool to find out where to change. Look at the longest path, and find if the time is used by logic or by wiring. If wiring you may try to change the location or do some pre-wiring, if logic you may move part of it into the previous or following pipeline stage. If you use a timing driven placement tool, you may just reduce the targeted cycle time and the tool may change placement for you to get to a better result. Finally from my experience the chip will most of the time run about 5% faster than calculated by the timing report.

Hope that gives you a different perspective of how to work with timing reports. 

transfer design to fpga and simulation will give you more accurate timing measure

If you want to find the accurate maximum delay of your design then I will recommend you use Synopsis ASIC flow instead of XIlinx. If your aim is to find the maximum frequency at which your design will work on FPGA, then you have to  test the design on fpga board by giving different clock at the input using function generator and capture the results on logic analyzer or chipscope.

Xilinx gives only estimated results to get an idea. However the accurate values  you can get after implementation only.

Please see synthesize and implementation reports in ISE.

is there anyone can help me about my problem ? the q : Write a verilog code to generate a 50Hz waveform with a duty cycle of 75%, on the A9 pin of the FPGA. Verify the period and duty cycle of the signal using an oscilloscope. I write a code but does not work well. How can I do that ?