Dear Raiyyan,

Your observations concerning the propagation delay time is possible. Any computational digital circuit is constructed based on its logic function which is in your case a modulo two addition of two binary numbers. The straight forward implementation of modulo two addition is by using X-OR gates which is also synthesized when using multipliers to implement the process.

The propagation delay time depends on the technology used to realize the logic gates.

If CMOS technology is used to implement the gates, then the propagation delay depends on the CMOS technology generation characterized by a minimum feature size. It is so that as the technology advances, the minimum feature size decreases and the as a consequence of the scaling the transistor size, the operating power supply voltage decreases.

It is so that the propagation delay time decreases as the size of the transistor decreases. To estimate the propagation delay time Td  for one logic stage, you can use the relation;

Td= L^2/ mu* VDD, where L is the channel length of the transistor, mu the mobility of charge carriers and VDD is the power supply voltage.

So, reduce Td one decreases L and operates the chip at the highest possible voltage

So, to reduces the delay time you can reduce he number of stages of the logic operations and use at the same time chips with advanced technology.

The first method depends on the algorithm of the logic function.

wish you success

dear Abdelhalim Sir, 

I am carrying out all the research work on my own and i am not associated right now with any institution or organization. So, I don't have access to some synthesis tools, except XILINX XST/ISE. And also, I am a undergraduate student trying to publish an article wherever I get a chance. So, being an undergrad, I am unaware of the concepts related to CMOS technologies other than a few fundatamentals. Nonetheless, I want to publish a paper on multipliers. So, without making any changes to the technology, is there any way I could reduce the delay for Spartan 3 FPGA in Xilinx. 

Dear Raiyyan,

I gave you an answer in my first comment but it seems that you did not take care of it.

In order to reduce the delay time you have to shorten the number of cascaded logic operations by redesigning the logic circuit. Pipe lining and parallel processing are used to increase the speed of operation. The idea is based on increase the hardware to decrease the processing time.

wish you success