I studied that NAND gate occupy less area than NOR gate. I need explanation or proof why it so?
Although in NAND gate pmos are in parallel and in NOR they are in series, so NAND gate is faster than NOR.
Dear Ritika Khurana ,
Just in brief:
NAND have equal rise and fall times. But a two input NOR has two PMOS connected in series. This requires more area to have good rise and fall times.
It depends on your desing or gate library....
1) Both NAND2 and NOR2 gates have four transistors each one. Therefore, if you set equal W and L for all transistors, both gates will occupy exactly the same area. However, timing behavior would be very different (for rise and fall transitions).
2) To make lage digital circuits, ussulay a gate library is used. The gate library has information about each gate that can be used in the circuit along with its timing behavior (delays) . To design (set W and L of transistors in each standard gate) the gate library, an inverter gate with minimum area but... that has balanced (equal) rise and fall delay is taken as design reference. This means that the other gates (including nand and nor gates) are designed in such way that their delays match with this simetrical inverter.
3) Remember that mobility of PMOS is less than mobilty of NMOS, thus, to match rise and fall delays in the inverter, on-resistances of each transistor should be similar: Tfall=RnCL = Trise= Rp*CL. The mobility differences is conmpenstated making Inverter PMOS greater than NMOS (lets said twice).
Then, simetrical inverter has: Wp=Wmin x 2 ; Wn= Wmin
4) The NMOS stack arrangement in NAND gate and the PMOS stack arrangement in NOR gate are sized up twice to match NAND and NOR gates delay with reference inverter delay. Therefore, we have:
for inverter (ref): Wp=Wmin x 2 ; Wn= Wmin
for nand: Wp=Wmin x 2 ;Wn= Wmin x 2
for nor: Wp=(Wmin x 2) x 2 ; Wn= Wmin
5) Areas are:
Ainv= (Wp+Wn)* L = 3 Wmin L
Anand= (2Wp+2Wn)* L= 8 Wmin L
Anor= (2Wp+2Wn)* L = 10 Wmin L
As can be seen, NOR area is greater than NAND area if a balanced timing behavior is required.
Dear Ritika Khurana,
Like the NAND gate, the NOR gate also has 2 PMOS and 2 NMOS transistors. They only differ in their placement, in case of the NAND gates the PMOS were in parallel and the NMOS were in series whereas in case of the NOR gates the PMOS are in series and the NMOS in parallel. The layout of NOR requires more area.
Dear Ritika Khurana,
The NAND Gate and NOR Gate has :
1. nMOS transistors: Two
2. pMOS transistors: Two
But, their placement differs.
1. The NAND Gate:
It consists of two series nMOS transistors between Output and GND and two parallel pMOS transistors between Output and VDD.
2. The NOR Gate:
The two nMOS transistors are in parallel to pull the output low when either input is high. The two pMOS transistors are in series to pull the output high when both inputs are low. Here, the NOR layout occupy more area than the NAND.
I hope I have answered your question.
With Best Wishes,
Samir G. Pandya
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