I tried one simple 4 tap FIR filter implementing on Nexys-4 board. The designed was directly based on the block architecture of a trasposed form 4 tap FIR. Using Vivado i got the simulation correctly but the on the FPGA I am not getting the correct results. What could be the reasons?
You should describe the situation in details to get useful answers.
What simulation mode did you use? How did you check the FPGA result is incorrect?
I never used the Xilinx tools, but, anyway, simulation results may differ from each other as well as from FPGA results (and also from your expectations) depending on the simulation mode chosen.
Do you want use an hdl language to describe the filter by yourself or do you wanna use an ip core?
http://electronics.stackexchange.com/questions/140410/verilog-fir-filter-using-fpga
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