Hello, From the literature I came to know that Zynq 7000 XADC has one dedicated analog channel and 16 auxiliary channels, and the maximum sampling rate is 1 MSPS. If I am using, both dedicated channel and 10 other auxiliary channels in independent mode, how the sampling rates will vary ? How is the auxillary inputs are shared between two ADCs ? Please help me in understanding this.
HI
I offer to see this article
"Implementation of Signal Processing IP
on Zynq-7000 AP SoC
to Post-Process XADC Samples "
The manual describes it in a lot of detail, but not very clearly. From this, not enough information can be had.
The chip is highly flexible, so many parameters affect the actual sample rate since each channel can have its own set of parameters, depending on the mode chosen.
The DCLK signal is divided by a selectable divisor (2-255) to ADCCLK, and then a number of ADCCLK cycles are required for conversion, settling time and averaging. Whether both ADCs are used in "Continuous sequence mode", or just one, is not stated.
In the simultaneous sampling mode, pairs are fixed, with the internal signals only available to ADCA and paired with nothing, so perhaps only ADCA is used in Continuous mode.
So, the short answer: sample rate is probably divided by total number of channels (11+ number of internal channels monitored), but other factors may also apply.
Olof
http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
Suppose my DCLK frequency is 20 MHz, and the divisor for ADCCLK is 4 (Maximum conversion rate is 193 KSPS now). Averaging is 16 samples and settling time is 4 ADCCLK cycles. In independent mode, it was stated that ADCA is dedicated to internal monitoring. So I understand all external auxiliary signals are handled by ADC B. If 11 auxiliary signals are connected, the sampling rate will be 17.5 KSPS. Is this the correct interpretation ? I simulated the same and got the wave forms as shown in attachment. The auxiliary channels are selected sequentially from 16 to 26.
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