I don’t think that the textbook scaling equations can be used for fair comparisons for recent nodes.
Hi,
That's a good question. You are correct that the textbook scaling equations can't be used as they vary significantly as compared to the actual scaling trends per silicon data in deep-submicron regime. Please refer to my paper (to be presented at ISCAS'21), "DeepScaleTool : a Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era", where in a spreadsheet based tool is proposed for accurate estimation of area, delay, power, and energy from 130 nm to 7nm.
Paper link - Preprint DeepScaleTool : A Tool for the Accurate Estimation of Techno...
Tool download link - https://sourceforge.net/projects/deepscaletool/
Hope it helps.
Dear Akhil Srinivas ,
For the comparison to verify the scaling rule it may not result in agreement with these scaling rules especially at these transistor dimensions.
The structure of the transistor changes at such nanometer devices such as using FINFET where the transistor changes from planar device to a 3-D device. Also the interconnects do not scale down.
It remains to compare the technologies by their rendition of the same implemented functions. I mean one compare them empirically.
Best wishes
Abdelhalim abdelnaby Zekry You are right. But I think the paper mentioned by Satyabrata Sarangi is designed out of silicon data and seems promising. Thank you for your answer.
It is not wise to compare an opinion with a research pair. You do not need to add your But sentence!!!
Akhil Srinivas Thank you for your kind words. I am glad that you find the tool useful.
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