Dear Yogendra,

Welcome, meeting again after long time. As the RTL is a high level description language which describes the digital circuit by signal flow among combinational logic functions between digital registers one has firstly to convert it to the level of logic gate level.

After which the logic gate level can be converted to the transistor level. Once converted to the transistor level one has the a complete circuit description as one already assumed certain implementation technology.Say CMOS .13 um technology file.

Such circuit can be solved by the circuit simulator Spice.

Design tools such as ISE from Xilinx and others can be used for such conversions.

For more information please loo at the link:

https://en.wikipedia.org/wiki/Xilinx_ISE

wish you success

I need the .sp file of the RTL code which I can simulate using HSPICE. But using Xilinx ISE I am not able to generate it. Could you please elaborate on this ? 

if you have VERILOG netlist you can convert it spice netlist using the software program

CATALYST DA. for more information please see the link:http://www.silvaco.com/products/digital_cad/verilog_netlist_spice_netlist_converter/catalyst_da.html

Best wishes.