I would like to "estimate" the thermal profile of a digital circuit at gate level. For instance, just consider temperature due to dynamic power dissipation. I have already computed the dynamic power profile based on gates switching activities and load capacitance. However I'm not sure how to continue to compute temperature.
I have found in literature the easy formula: T=Tamb+Rterm*Power. But I am not sure where to find the Rterm value (i.e. for the 65nm technology node). Furthermore I am not sure how to consider thermal coupling effects due to gates proximities in the layout.
An important question, It is very required to get the temperature profiles in chip.
Here i will introduce how to solve the problem.
In order to solve this problem you have to calculate the power dissipated in every gate say at the the location x,y in the chip. Assume that the obtained power is P (x,y) which is the power profile. The power profile may be dependent on the time but let us assume that its constant other wise the problem will be more complicated since it will be three dimensional.
-Then you have to work out a thermal model for the chip. You have to take into consideration the heat flow through the encapsulation. For example the chip is bonded to a metal frame with a metal legs. That is you have to model also at the same time the environment of the chip as it affects the disposal of the heat from chip.
- The model is approximately based on thermal conduction and storage by the materials conducting the generated heat flow to the ambient. It is so that every elemental volume is represented by a thermal resistance in parallel with a thermal capacitance. So, you can discretize the volume and model it by a lateral and vertical Rth-Cth network. Rth and Cth can be calculated as
Rth= delta x or delta y/ kth * area element
Cth= The specific heat csp * area element * delta x or delta y
where Kth is the thermal conductivity of the material
The network will be driven by the power sources P(x,y) calculated before acting in the nodes at the surface of the chip. Every point, in the network has a temperature relative to the reference node which is the ambient.
- there is a complete formal analog between the heat flow and the current flow
- You can solve this network by any network solver like PSPICE.
Since the properties of the materials are known, the dimensions are also known, then one can solve to get the rie in the temperature of every node relative to ambient.
Other solutions can be obtained by solving heat transfer equations.
The engineering approach is what i introduced here,
For more information please refer to the link:http://cache.freescale.com/files/analog/doc/white_paper/BasicThermalWP.pdf
wish you success
Hi,
Why didn't you use hotspot tool for temperature measurement? Temperature of all the structures of your design will be calculated in this way.
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