But, I have seen some options available from RTL compiler tool. However, i do not know the effectiveness.
RTL Compiler from Cadence has the option called "Build Power Model". It is used to estimate power dissipation.
Are you sure that internally it does not a synthesis to build the power model? I'm interested, let me know if you discover something useful. Thanks
No. It is part of synthesis flow only.
The thinking was that we are providing power feedback to aid in RTL development, much in the way synthesis provides timing and area feedback. And you can annotate power consumption back to the RTL. To get going, you'll first want to enable the RTL cross-probing with this attribute
set_attribute hdl_track_filename_row_col true /
Then you need to build the RTL power models. This of course uses your full SDC and utilizes the global synthesis engines so that the estimation is aware of how the logic will be structured and mapped for timing. The command to build the RTL power models is:
build_rtl_power_models [-clean_up_netlist] [-clock_gating_logic] [-relative instances] [-design design
Finally, to report power, the command is
report power -rtl_cross_reference [-detail] [-flat ] [> file]
You can follow the foll link or RTL compiler user guide.
http://community.cadence.com/cadence_blogs_8/b/ld/archive/2009/09/08/rtl-power-estimation
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