when we have verilog block as well as transistor, how can we configure the AMS simulation in CADENCE?
Zbigniew Jaworski
Create config view for the simulated cell -- I mean the test bench. Use AMS template when config is created. Next open the config view instead od schematic and start ADE L. In the setup replace Spectre with AMS. Next proceed as usual. There is one more and important step. You have to set up the Connect Rules that are responsible for converting signal from analog domain to digital and vice versa. Take care of H/L voltage levels (must correspond to VDD/GND), H/L threshold level and transition times. For details please consult the docs.
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