I have designed AXI Interconnect to connect 4 masters and 1 slave using SystemVerilog and Vivado Tool. The simulation stage of the design is working well. In the design, there are more I/O pins than the FPGA ZedBoard I/O pins.
Sorry, I don't understand the meaning of "maters" and "salve" as a quick look at the dictionary gives me probably wrong translations. But anyway: if you want to test a circuit for what you don't have enough pins you have to instrument multiplexing for groups of signals and split your test into test cases that fit to these groups.
Another solution could be to use the ARM-processor on the ZedBoard to emulate the I/O: your verilog design gets a synthesized testbench attached which is controllable (test case by test case) from the ARM core. This kind of test could be insufficient in terms of real-time.
If real--time test is required you unfortunately have to go for another platform than the ZedBoard.
No need for any dictionary sir. My question is more clear and there are 4 masters and 1 slave. Thank you for your helpful answer Peter Schulz..
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