You can provide a DC bias current or voltage by going to Simulation and then choose Discret Edge Port, it gives you the choice between S param, voltage and current and even the coordiantes for location.
One way would be to simulate the effect of applying a bias voltage to the tunable element in the planar reconfigurable element. For this end, you'd perform a parameter sweep for a key parameter that represents tunable effects in the tunable element. For instance, if your tunable element is a variable capacitor (varactor) in a phase shifter feeding the radiating elements, you could simulate the tunability by reducing the capacitance of varactor by a factor corresponding to the tunability value. If the capacitor is also modeled in a distributed form, then you could probably parameter sweep the relative permittivity of the ferroelectric dielectric in the capacitor design.
If you're modeling a distributed tunable element, it can get realy hard and extremely time and power consuming to simulate them in big model such as a reconfigurable antenna. This is usually because you need to generate a fine and dense mesh locally for your tunable lements and a coarse but massive mesh for your far field. One way to get around this would be to simulate your tunable elements separately and implement the effects with a more mess-effective approach. For instance, if you are using phase shifters of some sort with distributed elements, you could model it with delay lines for far field simulations.
I had to speculate what your tuning approach might be and provide some suggestions. Providing more information regarding your tunable element and the tuning mechanism in reality will make it easier for us to understand the problem and answer your question.
Thank you very much for your answer and I should implement it. Three thing still doubtful that one is the value of DC blocking capacitor is generally taken 100 pF as per data seen in various research papers. Is this data is variable or fixed (100 pF)? Second thing is that the PIN diode in forward biased then the value of series resistance is generally taken (~ 2-6 ohm) as per literature. Which series resistance value will be chosen either lower side or higher side? Third, what is the dimensions of discrete edge port taken to simulate the monopole structure?
Thank you for suggesting regarding tunable elements. My tunable element is PIN/Varactor diode but the biasing of the PIN/ Varactor diode in CST Microwave Studio is difficult. How can I provide the biasing lines for tunability of diodes?
You can provide a DC bias current or voltage by going to Simulation and then choose Discret Edge Port, it gives you the choice between S param, voltage and current and even the coordiantes for location.