Hi

One rough idea might be utilization of a pulse(clock) block and change the controller entirely into a synchronous machine. In this case, you can control the timing of each sub-system but the aforementioned clock. It is manifestation of the necessity of different clock-domains for different modules just like the sampler(As you concern) and the defuzzifier, inevitably that will lead to an asynchronous design.

Of course, in the case of pure coding as a m-file, out of the simulink, the easier and more efficient approach might be manipulation of the for loops, are which responsible for the sampling process.

Best