We have done tunneling current modelling for NW-NW junctions. You may go through similar calculations. Check our recent article:

https://www.researchgate.net/publication/261767953_Highly_Stretchable_and_Sensitive_Strain_Sensor_Based_on_Silver_Nanowire-Elastomer_Nanocomposite

Article Highly Stretchable and Sensitive Strain Sensor Based on Silv...

The accurate method is to consider the gate and oxide in the quantum transport simulation such as the attached publication. You can use Fig. 4 to find an estimate very easily based on your oxide thickness and material.

Article Optimum High-k Oxide for the Best Performance of Ultra-scale...

Dear Cong,

Do the vertical dimensions of the large area and small area the same eg the same gate thickness?. Are the two transistor  fabricated with the same fabrication steps?

Then on the average the the tunneling current across the gate will be proportional to area since one can assume the same areal tunneling current density.

However, perimeter and edge effect may affect this finding if the there is massive edge effect with extra leakage current. In this case one has to divide the current into Iarea and I per, Iarea= Jarea x A + Jper x Lperimeter, where A is the area and of the gate and Lperimeter is the circumference of the gate, J is the current density.

I think the model in this way will work properly. One needs only two areas in order to get Jaera and J perimeter.

wish you sucess

The tunneling in the overlap region at the source and drain will be different from the channel region because the band diagram on the silicon side of the oxide is different.  The approach described above using different length should allow you to model that.  Another effect may be error in estimating the actual length and width of your small devices.  The length you want to use is channel length, not the physical length of the gate.  The design length of the FET probably is different from either of these. In the width direction I would expect much edge effect in tunneling current, but the proper length for tunneling calculations may differ significantly from the drawn length.

I agree with Josef Watts. The short-channel effect associated with modulation of the space charge gate area, in which you need to consider 2-D effects. In particular, it will be observed modulation of the barrier height at the semiconductor-insulator along the channel under the gate. I not modeled for the MOS transistors, the current through the shutter, but for HEMT-transistors (AlGaAs/GaAs), I introduced an additional Schottky diodes and diodes on the basis of the heterojunction AlGaAs/GaAs, which included a different manner. However, in my case, the thickness of the wide band semi-insulator of Al0.3Ga0.7As was not thin, but the leakage current on the gate at voltages Vgate>1.1 volts  impact on I-V characteristics of transistors at low drain-source voltages at room temperature (nearby 0 voltage Vds, the current of the source-drain N-channel transistor was negative). If You need to take into account subtle effects in short channel transistor associated with the account of quantum effects in numerical simulations in the numerical model, consider the effect of tunneling when solving transport equations for charge carriers in a region under the gate of the transistor. It is a difficult task. I wish You success!