Basically you could get away with lower L and C values for the multilevel inverters as the size of the voltage steps decreases with the number of levels and the switching frequency increases. Although this (especially the increase in switching frequency) may also exhibit some side effects as all choke materials show some frequency dependency and some upper useable frequency limit.
So, whether the possible reduction in L and C really works out positively might depend on details of your circuitry and layout as well as on the properties of the chokes and capacitors chosen.
I would like to second Dr. Dreher, as the number of levels in the output waveform of the inverter increases, the low pass LCL filter cut off frequency increases and hence its inductor and capacitor values decreases inversely proportional to the cut off frequency. Since f = 1/2pi sqr LC so Land C are scaled down by f.
If the level changes say 8 times per cycle of the power frequency then the fundamental ripple frequency will be 4 times the 50 Hz which is about 200 Hz that must be removed by LCL filter.
You can find complete analysis of stepped sinewave inverter in the paper at the link where the harmonics and the total harmonic distortion are calculated. You can use the data available to design the harmonics filter.Article Computer-aided analysis of stepped sinewave inverters
Thank you all. I appreciate your answers. They are very helpful.
A special thanks to Pr. Abdelhalim Zekry for his article.
Just i want to know if there is a direct relationship, so that the idea behind it, is to create a comprehensive algorithm for LCL filter design whatever the voltage level of grid-tied multi-level inverter.