Hi all, In many research articles, it's been said that the near-threshold (NT) regime of a standard CMOS FET has exponential characteristics between drain current and Vth similar to sub-threshold (ST) operation (may be in slower rate) as well as the exponential behavior of process variation. But we know that generally, the near-threshold zone is bounded by ST at one end and super-threshold at the other end, leading to something in between (a moderate inversion). My question is do we have an accurate model for NT drain current ? Or still the standard ST Id model is valid for NTC regime ? (Here by referring to NT, I meant, the general situation of having 0.5 vdd for 1.2v standard devices where Vt s pretty closed to 0.5 but below !)   

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