I'm attempting to fabricate OFETs using p-type, Boron-doped silicon wafers as the gate electrode. My materials are p-type and my source and drain are made of gold. Before deposition of my conjugated polymer as the active layer, I do an ODTS treatment in order to make the wafer hydrophobic. Whenever I try and measure my devices, it seems that either the device is nonfunctional, or the device is shorted and the compliance value is exceeded. FYI, in order to probe the gate, I scratch off the SiO2 dielectric. Could these issues be due to using p-type silicon as the gate, or does the dopant for the gate electrode not matter as long as the silicon is somehow conductive?
Dear Michael,
welcome!
The doping of the silicon gate affects the the threshold voltage of the field effect transistor. Namely, it changes the work function of the silicon material which in turn affects the flat band voltage. The flat band voltage is the gate voltage that makes the energy levels of substrate flat. It is expressed by
Vfb= phi ms- qss/cox, phims= phim-phis
Vfb flat band voltage,
cox is the oxide capacitance,
phim is the gate work function
phis is the substrate work function,
qss is the electrostatic interface charge at the surface of the substrate.
Using the above expression one can calculate the flat band voltage and predict the its effect on the threshold voltage.
For more details please follow the book in the link: Book Electronic Devices
Best wishes
Dear Michael,
Do you use the prepattern p-doped silicon substrates? It means that source drain gold electrodes are already on the substrates.
Ideally n-doped silicon conducting electrode should be used to test p-type materials. The reason behind is that n-doped substrates generate electron charged to assist the current flow with p-type material OTFTs.
The layout of a transistor also play a crucial role too. I am not sure that how the layout you used such as channel length, channel width and thickness of the SiOx dielectrics. Your active layer thickness should be around 25 to 50nm range.
Hope it helps.
Xuhua
@Xuhua Wang thank you for the response! The wafers that we use are not prepatterned. We buy the doped wafers and evaporate gold on to them after spin coating our material. I'll use n-doped silicon from now on, thanks!
Dear Michael,
welcome!
The doping of the silicon gate affects the the threshold voltage of the field effect transistor. Namely, it changes the work function of the silicon material which in turn affects the flat band voltage. The flat band voltage is the gate voltage that makes the energy levels of substrate flat. It is expressed by
Vfb= phi ms- qss/cox, phims= phim-phis
Vfb flat band voltage,
cox is the oxide capacitance,
phim is the gate work function
phis is the substrate work function,
qss is the electrostatic interface charge at the surface of the substrate.
Using the above expression one can calculate the flat band voltage and predict the its effect on the threshold voltage.
For more details please follow the book in the link: Book Electronic Devices
Best wishes
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