Cadence/Valid GED schematic editor followed the Structured Computer-Aided Logic Design standard in a naming convention which identified the hierarchy level containing a particular net/component.

Any documentation (or even sample schematics showing net/part names in 2nd or subsequent level schematics) will be gratefully received.

The files are usually named logic,1,1, logic.2.1 and logic_cn.1.1, logic_cn.2.1 etc.