There are processors (PPC, ARM) for example where you can disable an entire cache. “Entire” can mean only the data or only the i-cache. Disabling part of a cache would be trickier, because you would need to have logic that allows altered addressing, which would add delay to the critical path on L1, less an issue for lower-level caches.

Thanks Philip. It was very helpful. Do you know how can I actually disable data cache on ARM? And if doing cuts off the power to it resulting in reducing in power consumed by the processor?

Are you sure the cache is contributing much to your power dissipation?

Osmond, if you do a google search on this you will find ARM datasheets and tech manuals.

Some examples

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0092b/ch04s04s06.html

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0092b/ch04s03s05.html

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/BABIGFEH.html

A thing you have to worry about is if your cut out the cache, your workload may take a lot longer to run, so total energy use could be higher than with the cache. Look up energy-delay product.

Another issue with disabling a cache on the fly is you have to be careful to flush the cash correctly – clean any dirty blocks.

An approach I briefly explored and not doubt there is more work out there if you look at it is putting DRAM into sleep mode when it is not being accessed. This can give you a bigger win, if the cache miss rate is low enough.

Conference Paper Initial Experiences with Dreamy Memory and the RAMpage Memor...

Dear Osman,

If you also have access to one of the Tilera's processors, such as the TILEPro64, you can disable the whole caching mechanism. We have done this in one of our papers.

Bests!

Thanks everyone.

Mark cache power consumption can be significant. I am using Intel Sandy bridge processors and cache power consumption can account up to 40% of the total CPU power consumption. Of course it depends greatly on the workload.