Please does anyone have an experience in implementing Decision Trees on FPGAs? I have read a couple of papers and emailed a couple of people but i haven't received very good feedback on how to go about the design and implementation. I have searched online for tutorials in this regard but can't seem to find much out there.
If you have experience in this, please can someone point me to the right direction either tutorials or where I can get substantial information on this. The area for implementation is not too important as I can always tailor it to my needs.
I am trying to design and implement it using the Xilinx vivid tools and implement it on the ZEDBOARD.
Any help is greatly appreciated.
Many thanks.
Sorry, I have no experience in digital design following a decision tree methodology. Just one thought: look-up-tables, as they are used as FPGAs' combinational logic, are in fact decision tree structures (see attached picture)
Decision trees is one of the algorithm and can be used for both python and fpga. With look up tables you can build a fpga combinational logic and can be used as memory.
https://ieeexplore.ieee.org/document/4211794
look here:
https://uweb.engr.arizona.edu/~rlysecky/courses/ece474a-10s/uploads/Main/lecture_asm.pdf
pages 13 and 14: decision tree logic for algorithmic state machine (ASM)
- Badges
- Science topic
- Similar topics
- Physical Sciences
- Optics