I'm not familiar with the proposed algorithm, however, _any_ algorithm can be implemented in digital hardware. You have to map: variables to registers/memory locations, operations to operational units (space] and a particular steps (time), and value assignments to data paths.

Whether this can be done efficiently depends on _internal parallelism_ of the algorithm, which must be estimated by data dependency analysis. The more parallelism, the better for hardware. Within the limits given by parallelism, various compromises between resources and performance can be done. The process is sometimes called high-level or behavioral synthesis.

It is a lot of difficult work, but where enough parallelism exist, superb implementations may be found.