I am facing a problem in VHDL via ModelSim. It is an error in my if-statement. if ((s(0) = c(0)) AND (NOT(x1(0)))) THEN I:= (others => '0'); end if; Here is my if-statement and the error is: "No feasible entries for infix operator "and"." But, after I tried to check the program I realized that the problem is with using (not gate). Maybe, there is another way of using it in vhdl. Could anyone help? I mean the first condition is Boolean and the next is std_logic operation.
Hi...
The following is the correct code segment. Use any one as per your requirement..
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if ((s(0)=c(0))) AND (NOT(x1(0))='1') THEN
I:= (others => '0');
end if;
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(or)
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if ((s(0)=c(0))) AND (NOT(x1(0))='0') THEN
I:= (others => '0');
end if;
----------------------------------------------------------------------
You do not need to write "(NOT(x1(0)))". Just check whether " x1(0) = '0'; "
You could use something like:
if (s(0) = c(0) and x1(0) = '0') then
I:= (others => '0');
end if;
In addition, i think that "I" is a vector signal, so you just try:
if (s(0) = c(0) and x1(0) = '0') then
I '0');
end if;