Suppose A is a 'tri'. A is being connected to the output of a module which is instantiated twice,in both the instances. In one instance the value of A will be 1'bz and in the other it will be 1'b1.What will be the A's value? Could you provide the reference in any textbook like Samir Palnitkar or the other?
Sundara Siva Kumar v
Generally wire is used for single output.
Tri is used for multiple output.
BOOKS:
1.A Verilog primer by J bhaskar.
2.DIGITAL DESIGN MORRIS MANO.
3.TEST BENCH CODE FOR VERILOG AND SYSTEM VERILOG BY JICKEN MANSON.
1 votes
0 thanks
Sundara Siva Kumar v
Please try by applying behavioural and structural type code format, After that this basic knowledge for solving the counters and other higher level applications.
CMOS MIXED CIRCUIT DESIGN -BAKER-WILEY.
1 votes
1 thanks
- Badges
- Science topic
- Similar topics
- Biological Science
- Bioecology
- Systems Ecology
- Landscape Ecology
- Connectivity
More Sai Krishna Garlapati's questions See All
Similar questions and discussions