The picture shown below is about Dickson charge pump from his paper.(On-Chip High-Voltage Generation in Integrated Circuits Using an Improved
Multiplier Technique).
As you can see from the image, the author says "In monolithic form,
C > Cs > 0.1C, typically".
Is this a reality or what we want? In design do we want Cs >> C? What is the purpose of that condition?
Dear Huan,
this is about UNDERSTANDING what you already gave:
"In MONOLITHIC form, C > Cs > 0.1C, TYPICALLY". Cs being the capacitance to the substrate.
Reading "monolithic" as "integrated circuit (on silicon)" you have to understand the properties of IC integration. Roughly spoken increasing C automatically increases Cs. And within "normal" semiconductor layout and processes C and Cs have a rather fixed ratio. That is what the citation is saying. It is not a condition, it is a pre-condition coming from monolithic integration constraints.
The clock voltage gets divided between C and Cs, so it becomes reduced by factor C/(C+Cs).
Trivial solution would be choosing C>>Cs, but when you consider clock loading prior to output voltage assuming its steady state that is proportional with (C+Cs) and frequency, you may consider keeping C as small as possible, but still considerably larger than Cs.
Using large C would be akin to short circuiting the clock generator.
Dear Huan,
Adding to Davor,
According to the straight forward analysis of the charge pump circuit, the voltage multiplication factor per stage is proportional to the capacitive division ratio C/(CS +C), SO, IT IS CLEAR THAT ONE HAS TO MAKE CS
Dear Huan,
this is about UNDERSTANDING what you already gave:
"In MONOLITHIC form, C > Cs > 0.1C, TYPICALLY". Cs being the capacitance to the substrate.
Reading "monolithic" as "integrated circuit (on silicon)" you have to understand the properties of IC integration. Roughly spoken increasing C automatically increases Cs. And within "normal" semiconductor layout and processes C and Cs have a rather fixed ratio. That is what the citation is saying. It is not a condition, it is a pre-condition coming from monolithic integration constraints.
Dear Davor, prof Abdelhalim and U.Dreher,
Thanks for the answers. There are some questions that are confusing me.
1. You all said that there is a voltage divider created by C and Cs. But why it is possible to consider a capacitive voltage divider here? As I understand for a voltage divider two elements are in series but here they don't seem to be the case. There are also diodes.
2. For the output resistance, Rs = N/(C+Cs)f where f is switching frequency of clocks.
I tried to increase C or increase f by a large factor to reduce output resistance but the result doesn't reduce anything noticeable at all.
Is there any thing hidden here?
Dear Huan
1. The voltage divider is effective for the 2 clock inputs. As both clocks (as well as Vin) are referred to Gnd (substrate) there is a path clock-C-Cs-substrate where the dividers are in effect.
2. Increasing C (which will increase Cs as well) and/or f is only effective if your clock signals are able to drive the increased load (as Davor already stated). So you'll have to check whether the voltages at the inter-diode nodes do not sagg when increasing either C or f, Otherwise you will additionally have to improve the clock drivers.
Dear U.Dreher,
1. I see your reasoning relating to two clocks. Yes, here two clocks are antiphase. When one clock goes to maximum the other drops to zero or ground. However, I am still don't understand why it is possible to consider C and Cs forming a voltage divider here.
Should a voltage divider have two or more elements and they are in series? Can we say that C and Cs are in series?
2. Relating to increase boosting capacitance C, in my Dickson charge pump C is an independent capacitor. I used it for simulation so changing C don't have any effect on Cs. If we increase C then it will take a long time to fully charge the capacitor. However, because clock frequency is not changed so these boosting capacitors are not fully charged. I will check it again and get back to you. Thanks again!
1. C and Cs ARE in series regarding the path from one of the clocks to ground.
2. When using a simulation program, you will have to adjust the driving characteristics for the clocks resp. Vin (especially the output resitance). On the other hand it is easy to 'measure' the voltage at the inter-diode nodes to assess the effectiveness of any measure.
BTW: if you have not already added a load resistor to the output: not it's the time (to be able to assess the output resistance in a fast and efficient way).
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