MOSFET is not in saturation reg even when vds> vgs-vth because vgd>vgs-vth. I am working on LNA in cadence. How to decrease the vgd?

My Question is when the VG is directly applied to gate of mosfet, in CS amp, though vds> vgs-vth is satisfied, the fet is not in saturation region because vgd> vgs-vth. How to decrease the vgd to...

21 August 2023 3,243 0 View