Jelili Oladayo Olawore

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Questions related from Jelili Oladayo Olawore

How can I debug my verilog code for concatenating the MSB to LSB of 2 4bit number?

It complains Input and Input is never used .The output is just displaying the concatenation of a[3] and b[3]. a = 1001 b = 1100 module stone(a,b,rslt);...

04 April 2015 2,339 4 View

Can anyone pls help me on how to design a clock frequency of a D- flip-flop to 40 GHz in verilog?

I designed a PRBS generator using verilog but i want to use the binary digit generated to test a communication medium that transmit at a data rate of 40Gb/s do i have to maximize my clock...

02 February 2015 2,398 4 View