I designed a PRBS generator using verilog but i want to use the binary digit generated to test a communication medium that transmit at a data rate of 40Gb/s do i have to maximize my clock frequency to 40GHz in order to transmit at that rate or it is irrelevant, i need some enlightment
Dear Abdul,
There is a difference between your Tx frequency and the Verilog clock rate.
- You need a Tx PHY (an analog block) that will transmit the data at 40 Gbit/sec.
Your analog designer need to design this for you, for sure not possible in Verilog.
- This PHY has a digital interface, eg 5 Ghz, 8 bit parallel, or 2.5 Ghz, 16 bit parallel,
or 1.25 Ghz, 32 bit parallel. This frequency and the parallellism is a negotitation, it
is a trade-off necessary to keep the digital manageable. Dont know what technology
you are in, and what speed it can run at, so I cannot be of any help here.
- Then, you need to design the PRBS using parallel logic on the lower clock. A PRBS is essentially a multiplier over a Galois field modulo a polynomial p(x). When you implement at 40 Ghz, it multiplies by x. When you implement at eg 1.25 Mhz (32x), it needs to multiply by (x**32), and there may be additional extra logic.
- So, in summary:
1. You need not run digital faster than your process allows, make it more parallel.
2. This complicates the design of the PRBS, but still manageable.
Cheers,
Henri.
Dear Abdul,
There is a difference between your Tx frequency and the Verilog clock rate.
- You need a Tx PHY (an analog block) that will transmit the data at 40 Gbit/sec.
Your analog designer need to design this for you, for sure not possible in Verilog.
- This PHY has a digital interface, eg 5 Ghz, 8 bit parallel, or 2.5 Ghz, 16 bit parallel,
or 1.25 Ghz, 32 bit parallel. This frequency and the parallellism is a negotitation, it
is a trade-off necessary to keep the digital manageable. Dont know what technology
you are in, and what speed it can run at, so I cannot be of any help here.
- Then, you need to design the PRBS using parallel logic on the lower clock. A PRBS is essentially a multiplier over a Galois field modulo a polynomial p(x). When you implement at 40 Ghz, it multiplies by x. When you implement at eg 1.25 Mhz (32x), it needs to multiply by (x**32), and there may be additional extra logic.
- So, in summary:
1. You need not run digital faster than your process allows, make it more parallel.
2. This complicates the design of the PRBS, but still manageable.
Cheers,
Henri.
ASIC implementation might be helpful to determine the frequency then try to pipelining to achieve maximum operating frequency
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