Indhu Sekar

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Questions related from Indhu Sekar

Hi I am using a cadence virtuoso to design a two stage CMOS OP-Amp. Facing issues with dc analysis in the hspiceD simulation?

I will paste the output log file and the netlist so that if anyone could point me the fix for the issue would be really helpful. ****Output Log*** Using:...

16 April 2023 4,413 2 View

Hi I am using a cadence virtuoso to design a two stage CMOS OP-Amp. Facing issues with dc analysis in the hspiceD simulation.

Hi I am Working on Cadence Virtuoso to design a 2 stage CMOS OP-Amp with first stage as differential amplifier and second stage to be a Common Source amplifier. I have to run a dc, ac and...

01 January 1970 5,851 1 View