Dear Muhammad,

as you already wrote, it's mostly personal preferences that decide about HDL usage. I have to say first that, personally, I prefer Verilog, so I might have missed some recent development of VHDL which might set off some of my points. I'll give some -partially subjective - advantages and disadvantages of VHDL:

Pro:

- more rigid syntax. In Verilog a common error is to assign a wrong-sized bit vector to a register, leading to some bits not being initialized or being assigned values other than expected. This just gives a warning by default while in VHDL it gives an error, avoiding hours of tracing errors.

Con:

- less syntactic sugar; in Verilog, e.g., you have always @(*) for sensitivity lists which captures all signals triggering changes of the output values while in VHDL you have to add every signal manually.

- syntax in general; VHDL is influenced by PASCAL and in many cases you have to type more for the same design. In my opinion, VHDL syntax is very clumsy.

I saw that you're asking regarding the introduction of an HDL into a curriculum. With that point, one could say that VHDL actually is the better choice due to its rigidity, making it easier to discover errors. Although I, personally, was quite confused by the entity - architecture concept in the beginning.

Best regards,

Johannes

What I got from your question is you want to know the advantages of VHDL over Verilog.

VHDL is strongly typed, deterministic and more verbose, need to add some extra lines of code to convert from one data type to another where as Verilog is weakly typed, more concise and only deterministic if you follow some rules carefully, with predefined data types.

VHDL syntax is non-C like where as Verilog is more C like.

VHDL has lot of programming constructs but lacks low level modeling capabilities for accurately representing hardware.Whereas Verilog is good at hardware programming but lacks in having higher level programming constructs.

FPGA designers prefer to use VHDL and is popular in Europe and Defence sector because low level modelling is not required in FPGA Design Flow where as ASIC designers prefer to go with using Verilog since they want register/gate transfer level of simulation for designing digital logic circuits,low level modelling capabilities needed for accurately capturing and representing the hardware and also Verilog has various behavioural extensions for simulation.

Also VHDL is better for writing testbenches, it is also more precise when defining mathematical operations. For VHDL synthesis the numerical operations are defined in package numeric_std; for Verilog they are new types in the language but there is some ambiguity in different versions of Verilog, things are just not defined very well there and if you take someone’s Verilog code you have to trust he did it correctly.

We can argue forever about which one is a better language, but a strong point has to be made that whatever hardware you can describe with one, you can describe with the other. There is no design that would present superior performance if written in A or B.

The same goes for verification, both languages have the same power to exercise a design.

It really boils down to a personal choice.

Right, Samuel Pagliarini - I was a bit surprised by some of the statements of Tariq M. Khan. I don't see why VHDL should be better suited for writing test benches. Arithmetic expressions are possible with Verilog, too, synthesis software can handle that for you (and is likely to perform better, as is the case for hand-coded assembly, too).

And regarding ASIC design, as far as I know it's common to use the synthesis primitive libraries of your selected foundry. It's rather pointless to design at transistor level as the efficiency greatly depends on the process used.

But back to the point - I still think that VHDL is better suited for teaching due to the more rigid syntax and the strong typing, which I forgot to mention. The latter reminds students that they're not programming and should think about data layout.

As for programming languages, it's more about concepts than about the actual language. And VHDL simply gives you less opportunities to do things wrong.