i have to write a testbench for iir filter using verilog. These testbench will contain a .txt file of ECG data.
I am not getting any idea....can anyone help me how to start?
Thanks
Weijia Lu thanks for your support.
I have a verilog code for LPF filter with cut off 100 Hz.
For testing the verilog code, I have to give some input(test bench) to that code.Filter is designed for 16 bit.
$readmemb used to read the memory containing binary numbers.btw i did this, next is how to go fo physical design?
It will be grateful if you help.
thanks
make a fake clock tick and feed bytes into your design. Please be aware of the wordlength, and I assume convolution is conducted in time domain, right?
I didn't know if you need to simluate clock jitter, afterall you need to decide when to detect the I/O from your memory; either in edge or in the center.
I would suggest use two clock tick, one for I/O and one for calculation.
Weijia Lu thanks for your effort man. it seems to be tough.i did not get anything what you said.
I assume you have one implementation already, like shown in this technical note?
https://www.xilinx.com/support/documentation/white_papers/wp330.pdf
I guess you need to prepare a time clock to put signal data on I/O, and similar/or different time clock with a phase shift for those delay elements (z-1s).
sir, i have verilog code of iir low pass filter, with test bench of input of ecg sampled data. I have simulated this code on vivado 2016.2 ide simulator but now i have to get it synthesized so i can go for physical design.I will be using cadence genus to synthesis this code.
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