As I have always understood power FET structures is that you get your power level by placing many smaller devices in parallel. These each have their gate capacitance in parallel, hence the capacitance grows larger as the device gets bigger. So at low frequency you still have the classical high impedance we were taught for a FET in electronics, but as frequency increases, that capacitance comes into play, decreasing the port impedance.

The low port impedances for large FETs are the main problem encountered in matching them to 50 Ohm. Have a look at transmission line transformers for the matching network. This allows for a 1:4 wideband transformation - so the 50 Ohm can be taken to a lower value that is easier to match to the device port impedance. Also useful when you have multiple devices in a balanced configuration.

This is also the reason why power levels goes down as operating frequency increases - cannot build a big device that mains an acceptable phase between the different parallel devices at very high frequencies.

I am sure there is someone on this forum that can explain the device structure in more detail.

Adding to Cornell's answer: Very large input capacitance together with resistive losses results in an input impedance with a small input resistance. The bond wires to the gates also add inductance, so input impedance ican even be purely resistive. This resistance is where the input power is absorbed, as opposed to low frequency behaviour where very little power is required to drive a field-effect transistor because the resistance is much smalle than the input series reactance.