I have designed a serial input based matrix multiplier architecture on FPGA. For smaller matrix size[ like 4x4,8x8] the resource utilization is very minimal. But when the matrix size goes beyond 16x16, the resource utilization exceeds way beyond hundred percentage. What I don't understand is, being the architecture stay fixed, how come the resource utilization increases with respect to input size.
Thanking you
Hi Anishchandran,
resouce utilization in this case increases superlinear (quadratic) because of the number of multiplications. But what I don't understand in your question: how can the architecture stay fixed and how can you then observe increased resource utilization? For observing increased resource utilization different synthesis and implementations runs are necessary.
Best Regards
Peter
Peter Schulz
Greetings sir
Thanking you for the reply
By mentioning 'architecture stay fixed' i meant that once we implemented an architecture on FPGA, then it does not dynamically change its architecture wrt input. For eg. in case of single precision floating point pipelined multiplier, each module in the architecture is defined for 32 bit width and corresponding logic resources are used. Obviously it is the same for entire algorithm execution process. So., how multiplying 2 matrices of 8 elements each, varies in terms of resource utilization to that of matrix with 16 elements. Because the input is fed serially and at one clock pulse, only two elements [of 32bit size due to SP] are multiplied irrespective of input matrix size.
If you don't mind, please clarify me on this regard
Thank you
@ Anishchandran: sorry, I didn't get it completely: how do you know about different resource utilization, if you don't rearrange your architecture?
What toolchain are you using? Could you please describe shortly what design steps you perform between size 8 and size 16?
Peter Schulz
Greetings sir
I designed a single precision floating point matrix multiplication architecture on FPGA using XILINX ISE. For up to 16x16 matrix sizes [ say A, B], the implementation utilizes very minimal fpga resources. But when I chose matrices A, B size as 64x64, the synthesis report shows more than 100% utilization of fpga resources.
Here the architecture is defined & designed for single precision. The method of inputting matrix A, B., whether it is 16x16 or 64x64 remains same i.e. serial input style. So at each clock cycle the architecture gets each of the multiplier and multiplicand data irrespective of size of the matrix. Then how come an increase in the size of the input matrices increases utilization of fpga resources?
Thanking you
@Anishchandran: are you instantiating the multipliers explicitly? Or do you leave the choice to the synthesis tool? If you leave it to the synthesis tool then it depends on your constraints whether the optimization will take place towards speed or area. If optimization is for speed the syntheziser probably will take all the multiplier instances the chip has available.
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