Transient simulation of PLL with Cadence (spectre, Eldo) or another SPCE like simulator at transistor level is too much time consuming, otherwise very accurate. EDA vendor did not have efficient solution to accurately simulate PLL with reasonable time. You may use Ultrasim but you may loose accuracy. Event driven approach is an alternative solution. You can have more informations in this paper : E. Ali et. al, "Simulative Characterization of the Stability for Second Order Voltage Switched CP-PLL", IEEE 56th Intl Midwest Symposium on Circuits & Systems, August 4-7, 2013, pp. 153 - 156

PLL is a bit difficult to simulate in standard Cadence Virtuoso because simulation time (on transistor level) tends to be tens of hours.

Therefore, i used Cadence Ultrasim for PLL development. It well-suited for mixed-signal simulation like AD-PLL or ADC. Minimal version to run Ultrasim is Cadence IC (Virtuoso) 6.0 and Cadence MMSIM 7.0

If you do not have MMSIM license, you should try any other FastSPICE simulator (GoldenGate etc.)

Tanner software ,

I believe before asking about "which Cadence version" you should make up your mind what you want to analyse: Usually you start with some high-level system analysis (eg. stability), this can be done by putting together a PLL model in s-domain and analyzing Bode-plots. Tools for that: eg. Mathcad, Matlab.

Next step would be to add clocking and switch to a z-domain model. Tools: Matlab, Simulink, Simetrix, or you may try already some behavioral modeling in VerilogA or VHDL. Only the last step should be block level design on transistor (or RTL level in case of digital control), where you need Spice level accuracy. Several tools exist to do that from several vendors. Finally the overall system can be checked by some fastspice simulator. Again several tools are possible, eg. Cadence Ultrasim or Synopsys XA.

Here you find a very comprehensive collection of (partly openAccess) design tools and models: http://www.circuitsage.com/

Hope this helped,

Christoph

Cadence Spectre RF is used to simulate the PLLs

NC SIM

But cadence toll is superior.

Use ADS from Agilent for Behavioral simulations

Cadence SpectreRF is most useful in such simulations.

Since the PLL is mixed-signal system, General theory of feedback system is not efficient to characterize behavior, Linear models are used to specify the design rules, but the  linear model covers small Validity area in the locked state only. But when using Cadence, Transistor level model at High frequency, due to high sampling ratio in divider block, mostly electrical simulator takes long time (Few hours to several weeks). Behavioral models are second choice to study the time domain behavior, even these are time taking, Efficient way of simulating a PLL at High frequency and analysis of the over non-linear pull-in process ,is the Event Driven approach based on the calculating the phase completing instant s of reference and divider signals. This technique has been applied to current switched charge pump PLL and has very interesting results, simulation time was few seconds, and rms error was less than 0.1%.   This method can be used for any application to realize PLL function, Frequency synthesis and Clock and date recovery.