What is the difference between Xilinx ISE and Vivado IDE? Which one is better?
In short:
* ISE/EDK are the old tools that are to be used for all Virtex-6 and older devices and that can be used for some small/middle-size Virtex-7 devices.
* Vivado is the new tool that only supports Virtex-7, UltraScale and all more recent families.
Xilinx explicitly said that they will not add support for older FPGA families into Vivado. So you still have to use ISE for them (e.g. Virtex-5).
The only FPGA family where you actually have a choice is some 7-series FPGAs that are supported by ISE and Vivado. both. My recommendation is to use Vivado for those. If you get a license from Xilinx, it works for ISE and Vivado both anyway.
Xilinx told me at a booth that they completely re-developed Vivado from scratch (starting about 5 years before it was released) with new algorithms for all steps (place and route, etc.) and new data bases for internal management. For instance, in ISE, each 'step' was actually a different binary tool that communicated via files with each other and ISE was actually mainly a GUI to connect them. In Vivado, all steps have the same view on a global data structure. That for instance allows you to trace back a signal that the post-place-and-route-static-timing-report identifies as your critical path, back to your HDL code. Additionally, the algorithms for Vivado are implemented with having the ever-growing size of FPGAs in mind. For instance, Xilinx told me that their placement algorithm has a complexity of O(n^4) (n being the number of elements to be placed) while at the same time producing a much higher reproducibility than the ISE algorithms (e.g. if you run P&R in ISE 5 times on a big design, you will get 5 different results with different timing scores). This won't happen in Vivado.
From my knowledge, Xilinx ISE is development tool for all family of Xilinx FPGA. Vivado is specified for more modern chips such as Zynq 7-series. Hope this help.
Xilinx ISE program is no longer supported by Xilinx for new version. But Xilinx ISE program is still used for all Xilinx family FPGA. Vivado program is new version and supported by Xilinx for new version. You can use only Artix 7, Virtex 7, Kintex 7 and another new series FPGA by Vivado. You can't use Artix, Virtex, Kintex 3,4,5,6 series by Vivado. And Vivado program is developed for synthesis, Implementation, Timing vb. So Vivado is better than ISE, if you don't use Artix, Virtex, Kintex 3,4,5,6 series FPGA.
In short:
* ISE/EDK are the old tools that are to be used for all Virtex-6 and older devices and that can be used for some small/middle-size Virtex-7 devices.
* Vivado is the new tool that only supports Virtex-7, UltraScale and all more recent families.
Xilinx explicitly said that they will not add support for older FPGA families into Vivado. So you still have to use ISE for them (e.g. Virtex-5).
The only FPGA family where you actually have a choice is some 7-series FPGAs that are supported by ISE and Vivado. both. My recommendation is to use Vivado for those. If you get a license from Xilinx, it works for ISE and Vivado both anyway.
Xilinx told me at a booth that they completely re-developed Vivado from scratch (starting about 5 years before it was released) with new algorithms for all steps (place and route, etc.) and new data bases for internal management. For instance, in ISE, each 'step' was actually a different binary tool that communicated via files with each other and ISE was actually mainly a GUI to connect them. In Vivado, all steps have the same view on a global data structure. That for instance allows you to trace back a signal that the post-place-and-route-static-timing-report identifies as your critical path, back to your HDL code. Additionally, the algorithms for Vivado are implemented with having the ever-growing size of FPGAs in mind. For instance, Xilinx told me that their placement algorithm has a complexity of O(n^4) (n being the number of elements to be placed) while at the same time producing a much higher reproducibility than the ISE algorithms (e.g. if you run P&R in ISE 5 times on a big design, you will get 5 different results with different timing scores). This won't happen in Vivado.
I heard vivado is more useful in creating IP core. You can convert your HDLs into softcore processor and you can call those architectures in to your other designs (Like a hierarchy ) and heard vivado support more hard core and softcore processors like DDR3. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_4/ug896-vivado-ip.pdf .
XILINX ISE/EDK are the old tools that are to be used for all Virtex-6 and older devices and that can be used for some small/middle-size Virtex-7 devices.
Vivado program is latest version and supported by Xilinx for new version. You can use only Artix 7, Virtex 7, Kintex 7, UltraScale and all more recent families of FPGA by Vivado. You can't use Artix, Virtex, Kintex 3,4,5,6 series by Vivado. And Vivado program is developed for synthesis, Implementation, Timing vb. So Vivado is better than ISE, if you don't use Artix, Virtex, Kintex 3,4,5,6 series FPGA.
Thanks
Dhruv Patel
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