The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays

According to (M.S. Hrishikeshi et. al. the 29th International Symposium on Computer Architecture)

The difference between pipeline depth and pipeline stages; is the Optimal Logic Depth Per Pipeline Stage which about is 6 to 8 FO4 Inverter Delays. In that, by decreasing the amount of logic per pipeline stage increases pipeline depth, which in turn reduces IPC due to increased branch misprediction penalties and functional unit latencies. In addition, reducing the amount of logic per pipeline stage reduces the amount of useful work per cycle while not affecting overheads associated with latches, clock skew and jitter. Therefore, shorter pipeline stages cause the overhead to become a greater fraction of the clock period, which reduces the effective frequency gains.

This chapter may be helpful 

http://http.developer.nvidia.com/GPUGems/gpugems_ch28.html

In short, pipeline is built of stages (processing blocks separated by registers). The more stages the larger pipeline depth.

All the best

http://cs.stackexchange.com/questions/67867/pipeline-depth-with-idle-stages