If you want to connect S and B you need put each set/pair in a deep n-well or triple well o niso layer. There are many names for the same thing.

usually for an NMOS bulk-drain connection , we have to isolate the bulk and this can be done by adding a deep N well  depending on your technology ... now , for PMOS you should do the same but with P well so unless you have a tipple well technology you cant do that.

Hi,

The name "diode connection" does not mean, that we have a p-n junction here. It is just the name adopted since it behaves similar to a diode (i.e. we have a nonlinear characteristic). For a PMOS the source corresponds to anode and the drain/gate to cathode. The bulk should be connected to the highest potential, but if you have an n-well technology, the bulk can be connected to source as well.

Thank you for your valuable reply's.. 

One of the reasons to connect the bulk in a PMOS to the highest potential is to avoid latch-up, which would probably result in the destruction of the device. However you can connect the bulk to other potentials if you want to change some characteristics of the MOSFET (Threshold voltage or linearity) as mentioned by Shivalal Patro. For the latch- up not to occur i.e. avoiding the source bulk parasitic junction from being forward biased, you need to guarantee that at all time Vsb < Vth (threshold voltage for that junction). Thus if you connect Source to Bulk Vsb = 0 and no latch-up will occur. This connection is used because it removes the first order effects of one of the largest contributor to non linearity which is the body effect. That way id = K w/l (Vgs-Vth)^2 instead of id = K w/l (Vgs-Vth)^2 [1+A(Vds-Vdsat)] where A is a channel-length modulation parameter. Without body effect id no longer depends on Vds.

I hope this helps

Regards

Just a small note: using the highest potential for the bulk connection in your PMOS is OK, of course.  You could also use a slightly lower potential ("VDD_2") than VDD if you ensure that S or D of your PMOS are kept lower than VDD_2.

As Tomasz Kulej correctly states: "The name "diode connection" does not mean, that we have a p-n junction here. It is just the name adopted since it behaves similar to a diode (i.e. we have a nonlinear characteristic)."

Indeed there is no forward-biased junction here (with bulk connected to source), but you are indeed looking at the non-linear behavior of the saturated MOS transistor, with the drain current flowing through the MOST's channel as usual. Simply here any increase in the drain voltage will also result in a "diode-like" increase of drain current. When gate voltage is above threshold (VG-VTO)>0  (or strong inversion), the current ID of the gate-drain connected transistor corresponds to the quadratic law ID ~= K (W/L) (VG-VTO)^2, where now VG=VD due to the gate-drain connection. As noted by Diogo Miguel Caetano, the body effect disappears due to the source-bulk connection VSB=0 (Note that the channel length modulation effect does actually not disappear). Finally when (VG-VTO)

Adding to the above when connecting the drain to gate to form a two terminal device to work as a rectifier it  is advisable to connect the Bulk terminal to the source. In this way you get always the smallest cut-in voltage of device which is advantageous in case of relatively small AC voltage to be rectified. This will increase the output voltage and conduction angle of the rectifier.

In case of connecting the bulk terminal to the most positive voltage in case of PMOS , then in some instants of the waveform the Bulk source gets reverse biased and this leads to increasing of the threshold voltage of the transistor and consequently the cut-in voltage of the diode. This type of operation is not required as you want to maximize the output voltage of the rectifier.

You can your self be sure of this phenomenon by simulation.

So in conclusion, it is better to connect the bulk B to the source for this application.

for a better performance of the PMOS it is recommended to connect the bulk to the source. because by this way the buddy effect is totally neglected. If you want to determine which of the two pairs of the transistor terminal is the equivalent diode terminals, I refer you to the physic of the transistor. It will be clear that in a PMOS tr. the source acts as anode and the gate acts as the cathode. and the |VTH| of tr is equivalent to the V_gama of diode.

I guess you are working on a classical twin-well CMOS technology where the PMOS is made in an N-well and this is embedde in a P-type substrate. If you use the PMOS as a pseudo-diode, the Gate must be connected to the Drain of the PMOS. The Gate/Drain is then the cathode of your pseudo-diode and the Source is the anode.

The problem with the N-well Bulk of the PMOS is that this Bulk is also connected to both Drain and Source by a real P/N junction diode. In order to prevent these real diodes from becoming forward biased (which can provoke lacth-up) The Bulk must in all circumstances remain at a higher voltage than both the Drain and the Source voltage minus a diode voltage.

In forward bias (conducting pseudo-diode) connecting the Bulk to the Source is OK since the Drain is then at a lower voltage than the Source.

In Reverse bias however (blocking pseudo-diode), the Drain can go higher than the Source and the Bulk can no longer be connected to the Source since then the real Drain/Bulk junction diode becomes forward.

Hence, the Bulk of the PMOS pseudo-diode is normally connected to the highest (supply) voltage or at least to a voltage higher than the highest Drain or Source voltage. This is safe but not ideal since the bulk-effect will increase the threshold voltage of the PMOS.

This is the case for classical twin-well technologies and also for triple-well technologies. It can be different for SOI technologies.

Note that some SPICE models do not include the real S/Bulk and D/Bulk diodes in the transistor model and most do not include the Bulk/Substrate diodes.

Hi,

you can follow this paper to control the body.

Efficiency-enhanced CMOS rectifier for wireless telemetry

C.-L. Chen, K.-H. Chen and S.-I. Liu

Thanks

Ammad

First have a look on your DRM. If it is possible to do it on the technology you are using, you will find the information there.

Herman's answer explains it clearly.

Just to add a few quick points:

In case of a rectifier, the voltage on the drain side will go higher than the source for some portion of the negative cycle of the input (though by definition, it is not drain any more, lets still call it "drain" by convention as it is tied to the gate). 

Basically there is not a short answer as to which side is a better option to connect your the terminal to.

- For a simple design where you do not care much about the turn-on voltage of your diode (Vth of PMOS), simply connecting it to the output side (source) is the safest way to go.

-If your input level is small and you want to partially cancel the threshold of the diode connected PMOS switches/diodes, you may want to tie it to a lower voltage. The catch is, such static threshold cancellation (i.e., connecting body to a low voltage) although helps in forward conduction cycle, increases the leakage (due to lower Vth) in reverse conduction. In extreme cases, what you lose is more than what you gain. The best approach is to set the body voltage dynamically and according to S-D voltage. Take a look at differential-drive rectifiers where you can connect the gate and the body of switches to the complementary (180 shifted version) of input. 

Short answer:

1- High input level where turn-on voltage is not a concern: connect to output side(intermediate output for multi-stage)

2- Small input level where turn-on voltage is to be (partially) cancelled: connect to lower voltage and watch for latch-up, or tune it dynamically.

Thank you for all your responses...