There are three edge-triggered flip-flops namely SR, D and J-K that are used in digital logic circuits and every flip-flop has its own operation. State that how these flip-flops can have an effect on the performance of synchronous systems, and also discuss which flip-flop gives better performance
Article The Use of A Simple Methodology for Flip Flop Conversion as ...
Michel Owayjan's attachment on flip flops is a good description of the different types of flip flop logic. I have a few comments though.
True SR flip flops are not found very often since they have one undefined state where both inputs are true. This is generally not a good thing since you don’t know what will happen if this occurs. The JK solves this by defining this state.
Don’t make the assumption that all flip flops are edge triggered. Many are but there are also master-slave flip flops and latches. The master-slave stores the input on one edge of the clock and transfers the stored data to the output on the other edge. A latch allows the data to flow through the flip flop while the clock is true but stores it when the clock transitions to false. The timing for each of these is different and in the case of the latch the logic is not just that of a storage device since the output can change to follow the input as long as the clock is true.
I’m not sure what you mean when you ask “discuss which flip-flop gives better performance”. If you’re asking which one works better from a logic design perspective, it depends on what you’re designing and what function the flip flop will do. If you’re asking which one is faster or has better timing you need to look at the specs for the device in logic family you’re using. A 74HC series flip flop is going to be much slower than a similar flip flop in a gate array.
Sir, Chris Dewitt and Michel Owayjan
Thanks for your early reply and usefull knowledge.
Infect the question is that how these all types of Flip-Flops effects performance of a synchronous circuit. what i thins time delays, set time , hold times ect. actualy effects the performance . if it is true than which one of them effects the performance more.
Zahoor -
There is no set answer to this question. It will depend on the specifics of the design and the logic family used. Generaly the logic family (74HC, 74AC, gate array or other) is picked because of the general needs of the application, you do an inital design and then analyze ALL the timing. If everything works fine, other wise you find ways to change the design to solve the problem.
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