Please provide complete files. Without package and signal declarations I cannot say anything.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY pwm IS
GENERIC(
sys_clk : INTEGER := 50_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 100_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 16 --bits of resolution setting the duty cycle
);
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC ); --pwm inverse outputs
END pwm;
ARCHITECTURE logic OF pwm IS
CONSTANT period : INTEGER := sys_clk/pwm_freq; --number of clocks in one pwm period
SIGNAL count : INTEGER RANGE 0 TO period-1 := 0; --array of period counters
SIGNAL half_duty_new : INTEGER RANGE 0 TO period/2 := 0; --number of clocks in 1/2 duty cycle
SIGNAL half_duty : INTEGER RANGE 0 TO period/2 :=0; -- half duty value
BEGIN
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --asynchronous reset
count
What is exactly the problem? Is the value produced wrong? This may be a result of too complex expression (division, multiplication, etc.). You may try to divide the single expression in to several simpler ones. Also you may try to use parenthesis to explicitly enforce order of operation execution.
All the operands are integers eventually. The question is what's the desired order of operations in the "period/(2**bits_resolution)/2"
If that is resolved then BODMAS- Brackets Of Division Multiplication Addition Subtraction - is the order that in (hopefully) followed by the compiler or user...
As long as I don't how the original formula looks like i can't suggest a solution.
So, Dear Ayman Yousef. Please use your preferred office equation editor and tell us what actually are you going to implement. If you want an answer formulate your question as precisely as possible.
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