Is IKW75N60T an IGBT of fourth generation? Please send a link to the datasheet!

http://www.infineon.com/dgdl/IKW75N60T+Rev2_6G.pdf?folderId=db3a304412b407950112b408e8c90004&fileId=db3a304412b407950112b42890113e25

The "tail current" is generally defined as that part of the collector current (Ic) waveform where Ic continues to flow after an initial abrupt fall; looking at the waveform of Ic on a scope, the "tail current" starts when the rate of change of collector current distinctly reduces. You can read about the reasons for the existence of tail current in many articles from the major manufacturers. Depending on the technology of the IGBT, tail current (magnitude and duration) can have a strong dependence on temperature.

Tail current adds to the turn-off losses within the IGBT, because this current is occurring when Vce is high. In the case of clamping inductive load switching, the IGBT Vce has increased to the power supply rail (or higher, depending on stray inductances and if any snubber circuit is present) the moment the device begins the turn-off process.

The datasheet you provided does not specify the characteristics of the tail current. All it mentions is that the values of turn-off energy include tail current losses; refer to page 3, under the section "Switching Characteristic, Inductive Load at Tj=175C. Under conditions of bus voltage of 400VDC, load=75A (and other specified conditions relating to gate drive), the stated energy lost each turn-off event is 2.9mJ. It is interesting to note for this device that the turn-on loss is the same at 2.9mJ (including that due to diode reverse recovery characteristic of the anti-parallel diode of the same IGBT device). So total switching loss for the switching device (not the device being used as a diode!) is 5.8mJ.

A good question is: at what frequency will the switching loss equal conduction loss? This can provide a useful indication of an upper limit for switching frequency of a particular device. Assuming duty-cycle of 50%, and the same supply voltage, load, and gate-drive conditions as per the datasheet, we find that conduction loss is:

Pcond = 0.5 * 75A * Vce(sat) = 0.5 * 75A * 1.9V = 71.3W.

And the switching frequency (Fs) where switching loss equals conduction loss is:

Fs = 71.3W / 5.8mJ = 12.3kHz.

Is this a realistic situation? Well, let’s consider the thermal situation. Under these conditions, the total device power loss is 142W. Given that thermal impedance from junction to case is 0.35 K/W, and assuming additional thermal impedance due to heatsink insulating sheet of about 0.2K/W, means total thermal impedance from junction to heatsink of 0.55K/W, so that the IGBT silicon junction will be hotter than the heatsink by: 0.55K/W * 142W = 78K. To keep junction temperature below 125C, the heat-sink temperature therefore must be kept below 125 – 78 = 47C. So, yes, this is quite realistic as a maximum power dissipation for this device, but obviously as heatsink temperature increases above 47C, the 75A load current needs to be reduced automatically to maintain device temperature at or below 125C.

For a given IGBT device, the only way to eliminate the tail current is to place the IBGT in a circuit where the IGBT does NOT switch Ic off, ie: Ic falls to zero due to the circuit in which the IGBT is operating. For example, resonant loads naturally force the current to zero. There are many circuits which can do this, they are generally grouped under the heading of "soft-switching" circuits. However, when compared to "hard-switching" PWM circuits, these "soft-switching" circuits generally have more components, are more complex to control, and both these factors increase their cost - however, they do reduce losses and hence are more efficient.

Thanks Fabio :) I am working in ZVS switching mode only. Now the problem is whenever we use a parallel mosfet with IGBT for ZVS switching, at the time of switching of mosfet there is a high dV/dt across IGBT also, due to this a current flows through IGBT's miller capacitance via gate resistance of driver. Now this current is high enough to generate a high gate voltage to trigger the IGBT. Interesting thing is this false triggering voltage is higher at turn off time if IGBT is not completely off (i.e some tail current is present). so please give me solution for this .

Thanks a lot for such a well explained answer.

Hello Vaibhav, sorry I do not have an explanation for why the "false trigger voltage" is higher when there is some tail current present at time of IGBT turn-off. I suspect it will have something to do with increased miller current (drain to gate) flowing into the resistance of the gate driver, due to increased miller capacitance. Possible explanation is that the internal regions of the IGBT will have different charge densities that change as the tail current reduction process progresses, and I suspect that the charge-free regions that support the blocking voltage have sizes that start off short and gradually increase as the tail current is extinguished. (short distance means large capacitance hence larger miller current).

But for practical reasons, I suggest you simply handle this situation by combinations of:

1. Reducing IGBT gate driver resistance during turn-off.

2. Increase delay time from IGBT turn-off to MOSFET turn-off.

3. Reduce dv/dt at turn-off, but note there is some evidence to suggest that the tail current process needs a driving voltage, so ZVS (low dvdt at turn-off) may not be as effective for IGBT as it is for MOSFET.

Dear Vaibhav,

You may provide a negative supply of typically -5 V along with +15/+12 V (generally required to drive the IC) to amplification and isolation IC used in gate-drive circuit. This way you can ensure a propoer commutation of IGBT even during the presence of tail current.

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