I am doing my PHD in analysis and design of operational amplifier through SET, so my first step is to show the advantage of SET. Therefor need help to simulate the SET
Which software is used and how it is simulated ?
Mustafa F. Ali
Look for a Verilog-a model of the SET, and put it in Cadence IC Design if you want to simulate circuits in addition to single device.
the verilog-a model may be found in nanohub.org
https://nanohub.org
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