In a paper I found the analytical equation of gate capacitance relating to the process parameter fin width, whereas some others showed some different equations excluding fin width.
I am confused with how fin width can be significant or how it is related to gate capacitance.
Can anyone please tell me about any method of capacitance modeling, considering the effects of process parameters (especially the fin width)?
You can see this website, You can find your question.
http://www.ecse.rpi.edu/frisc/theses/CampbellThesis/chapter6.html
There are some papers with process variations in TG Finfets. probably you ll be able to find a specific paper on it. however an interesting paper link is attached. let me know if you have problems in downloading pdf.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6188775
Thanks a lot... reading the abstract, I think it'll help me.But I dont't have access to download the paper.
Actually FinFET possess capacitance of different kinds. Each of them has its own dependency on the geometry as well as analytical model for it.
You will get the detail of them in the attached papers.
Okay. There you go for pdf file of above paper. I hope you already got your answer and this will help you more.
Hi,
The following link can probably help your affiliation company or univ. for a trial, as you mentioned earlier of having problems in downloading pdf files (because of no access to IEEE)
See if Your Organization Qualifies for a Free Trial of IEEE Xplore.
http://forms1.ieee.org/FreeTrial.html?LT=tryIEEExploreprintad
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